1 radiation hardened high speed, monolithic digital-to-analog converter hs-565brh, hs-565beh the hs-565brh, hs-565beh are fast, radiation hardened 12-bit current output, digital-to-analog converters. this part replaces the hs-565arh, which is no longer available. the monolithic chips include a precision voltage reference, thin-film r-2r ladder, reference control amplifier and twelve high-speed bipolar current switches. the intersil dielectric isolation process provides latch-up free operation while minimizing st ray capacitance and leakage currents, to produce an excell ent combination of speed and accuracy. also, ground currents are minimized to produce a low and constant current throug h the ground terminal, which reduces error due to code-dependent ground currents. hs-565brh, hs-565beh die are laser trimmed for a maximum integral nonlinearity error of 0.25 lsb at +25c. in addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient. specifications for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-96755 . a ?hot-link? is provided on our website for downloading. features ? electrically screened to smd # 5962-96755 ? qml qualified per mil-prf-38535 requirements ? total dose . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad (si) (max) ? dac and reference on a single chip ? pin compatible with ad-565a and hi-565a ? very high speed: settles to 0.50 lsb in 500ns max ? monotonicity guaranteed over temperature ? 0.50 lsb max nonlinearity gu aranteed over temperature ?low gain drift (max., dac plus reference) . . . . . . . . . . . . . . . . . . 50ppm/c ? 0.75 lsb accuracy guaranteed over temperature ( 0.125 lsb typical at +25c) applications ?high speed a/d converters ? precision instrumentation ? signal reconstruction figure 1. functional diagram ref out vcc 43 + - 19.95k ref in 10v 6 5 ref gnd + - 3.5k 3k iref 0.5ma -vee pwr gnd 712 24 . . . 13 msb lsb (4x iref x code) 20v span 10v span out io dac 9.95k bip. off. 8 5k 5k 2.5k 11 10 9 may 7, 2012 fn4607.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2003, 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
hs-565brh, hs-565beh 2 fn4607.4 may 7, 2012 pin configurations hs1-565brh, hs1-565beh mil-std-1835 cdip2-t24 (sbdip) top view hs9-565brh, hs9-565beh mil-std-1835 cdfp4-f24 (ceramic flatpack) top view 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 nc nc vcc ref out ref gnd ref in -vee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in (msb) bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in (lsb) bit 2 in bit 7 in bit 9 in 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 nc nc vcc ref out ref gnd ref in -vee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in bit 2 in bit 7 in bit 9 in (lsb) (msb) ordering information ordering number part number part marking temp. range (c) package (pb-free) pkg. dwg. # 5962r9675502v9a hs0-565brh-q +25 5962r9675502vjc hs1-565brh-q q 5962r96 75502vjc -55 to +125 24 ld sbdip d24.6 5962r9675502vxc hs9-565brh-q q 5962r96 75502vxc -55 to +125 24 ld flatpack k24.a hs9-565brh/proto hs9-565brh/proto hs9- 565brh /proto -55 to +125 5962r9675503v9a hs0-565beh-q +25 5962R9675503VJC hs1-565beh-q q 5962r96 75503vjc -55 to +125 24 ld sbdip d24.6 5962r9675503vxc hs9-565beh-q q 5962r96 75503vxc -55 to +125 24 ld flatpack k24.a note: these intersil pb-free hermetic packag ed products employ 100% au plate - e4 te rmination finish, which is rohs compliant an d compatible with both snpb and pb-free soldering operations.
hs-565brh, hs-565beh 3 fn4607.4 may 7, 2012 burn-in bias circuit notes: d1 = d2 = d3 = in4002 or equivalent f0 to f11: vih = 5.0v 0.5v vil = 0.0v 0.5v f0 = 100khz 10% (50% duty cycle) f1 = f0/2 f7 = f0/128 f2 = f0/4 f8 = f0/256 f3 = f0/8 f9 = f0/512 f4 = f0/16 f10 = f0/1024 f5 = f0/32 f11 = f0/2048 f6 = f0/64 radiation bias circuit note: power supply levels are 0.5v definitions of specifications digital inputs the hs-565brh, hs-565beh accepts digital input codes in binary format and may be user connected for any one of three binary codes. straight binary , two?s complement (see note below), or offset binary. accuracy nonlinearity - nonlinearity of a d/a converter is an important measure of its accuracy. it descri bes the deviation from an ideal straight line transfer curve drawn between zero (all bits off) and full scale (all bits on). differential nonlinearity - for a d/a converter, it is the difference between the actual output voltag e change and the ideal (1 lsb) voltage change for a one bit ch ange in code. a differential nonlinearity of 1 lsb or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. settling time settling time is the ti me required for the outp ut to settle to within the specified error band for any input code transition. it is usually specified for a full scale or ma jor carry transition, settling to within 0.50 lsb of final value. drift gain drift - the change in full scal e analog output over the specified temperature range expressed in parts per million of full scale range per c (ppm of fsr/c). gain error is measured with respect to +25c at high (th) and low (tl) temperatures. gain drift is calculated for both hi gh (th - +25c) and low ranges (+25c - tl) by dividing the gain error by the respective change in temperature. the specification is the larger of the two representing worst case drift. offset drift - the change in analog outp ut with all bits off over the specified temperature range expressed in parts per million of full scale range per c (ppm of fsr/c). offset error is measured with respect to +25c at high (th) and low (tl) temperatures. offset drift is calculated for both high (th - +25c) and low (+25c - tl) ranges by dividing the offset error by the respective change in temperature. the specification given is the larger of the two, representing worst case drift. c3 d3 +10v 1 4 5 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 2 3 6 7 nc c1 d1 +15v c2 d2 -15v f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 nc vcc ref gnd ref out ref in -vee bip off out 10v span 20v span pwr gnd bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 +15v 1 4 5 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 2 3 6 7 nc nc vcc ref gnd ref out ref in -v ee bip off out 10v span 20v span pwr gnd bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 -15v +10v +5v digital input analog output straight binary offset binary two?s complement (note) msb...lsb 000.... 000 zero -fs (full scale) zero 100.... 000 0.50 fs zero -fs 111.... 111 +fs - 1lsb +fs - 1lsb zero - 1lsb 011.... 111 0.50 fs - 1lsb zero - 1lsb +fs - 1lsb note: invert msb with external inverter to obtain two?s complement coding
hs-565brh, hs-565beh 4 fn4607.4 may 7, 2012 power supply sensitivity power supply sensitivity is a meas ure of the change in gain and offset of the d/a converter resulting from a change in -15v or +15v supplies. it is specified under dc conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of fsr/%). compliance compliance voltage is the maximum output voltage range that can be tolerated and still maintain its specified accuracy. compliance limit implies functi onal operation only and makes no claims to accuracy. glitch a glitch on the output of a d/a converter is a transient spike resulting from unequal internal on-off switching times. worst case glitches usually occur at ha lf scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. for example, if turn on is greater than turn off for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. matched switching times and fast switching will reduce glitches considerably. applying the hs-565brh and hs-565beh op amp selection the hs-565brh, hs-565beh current output may be converted to voltage using the standard connect ions shown in figures 2 and 3. the choice of operational amplifier should be reviewed for each application, since a significant trade-off may be made between speed and accuracy. remember settling time for the dac-amplifier combination is: where t d , t a are settling times for the dac and amplifier. no trim operation the hs-565brh, hs-565beh will perform as specified without calibration adjustments. to operate without calibration, substitute 50 ? resistors for the 100 ? trimming potentiometers: in figure 2 replace r2 with 50 ? ; also remove the network on pin 8 and connect 50 ? to ground. for bipolar operation in figure 3, replace r3 and r4 with 50 ? resistors. typical unipolar zero will be 0.50 lsb plus the op amp offset. the feedback capacitor c must be selected to minimize settling time. calibration calibration provides the maximum accuracy from a converter by adjusting its gain and offset errors to zero. for the hs-565brh, hs-565beh, these adjustments are similar whether the current output is used, or whether an external op amp is added to convert this current to a voltage. refer to table 1 for the voltage output case, along wi th figure 2 or 3. calibration is a two step process for each of the five output ranges shown in table 1. first adju st the negative full scale (zero for unipolar ranges). this is an offset adjust which translates the output characteristic, i.e., affects each code by the same amount. next adjust positive fs. this is a gain error adjustment, which rotates the output characteristic about the negative fs value. for the bipolar ranges, this approach leaves an error at the zero code, whose maximum values is the same as for integral nonlinearity error. in general, on ly two values of output may be calibrated exactly; all others must tolerate some error. choosing the extreme end points (plus and mi nus full scale) minimizes this distributed error for all other codes. t d () 2 t a () 2 + vo - + dac out 9 10 11 20v span 10v span 2.5k 5k 5k c 9.95k io 24 13 msb lsb . . . . . code input dac (4 x iref -vee pwr gnd 7 x code) iref 0.5ma hs-565brh 3k 3.5k 19.95k + - 10v 3 4 vcc + - 6 5 ref gnd ref in ref out r2 100 ? 8 bip. off. +15v -15v r1 50k ? 100k ? 100 ? figure 2. unipolar voltage output r (see table 1) vo - + dac out 9 10 11 20v span 10v span 2.5k 5k 5k c 9.95k io 24 13 msb lsb . . . . . code input dac (4 x iref -vee pwr gnd 7 x code) iref 0.5ma hs-565brh 3k 3.5k 19.95k + - 10v 3 4 vcc + - 6 5 ref gnd ref in ref out r4 100 ? 8 bip. off. r3 100 ? figure 3. bipolar voltage output r (see table 1)
hs-565brh, hs-565beh 5 fn4607.4 may 7, 2012 settling time this is a challenging measurement, in which the result depends on the method chosen, the precision and quality of test equipment and the operating configuration of the dac (test conditions). as a result, the different techniques in use by converter manufacturers can lead to consistently different results. an engineer should understand the advantage and limitations of a given test meth od before using the specified settling time as a basis for design. the approach used for several year s at intersil calls for a strobed comparator to sense final perturbations of the dac output waveform. this gives the lsb a reasonable magnitude (814mv) for the hs-565brh, hs-565beh, which provides the comparator with enough overdrive to establish an accurate 0.50 lsb window about the final settled value. also, the required test conditions simulate the dacs environment for a common application - use in a successive approximation a/d converter. considerable experience has shown this to be a reliable and repeatable way to me asure settling time. the usual specification is based on a 10v step, produced by simultaneously switching all bits from off-to-on (ton) or on-to-off (toff). the slower of the two cases is specified, as measured from 50% of the digital input transition to the final entry within a window of 0.50 lsb about the settled value. four measurements characterize a given type of dac: (cases (b) and (c) may be eliminated unless the overshoot exceeds 0.50 lsb). for example, refer to figures 4a and 4b for the measurement of case (d). procedure as shown in figure 4b, settli ng time equals tx plus the comparator delay (td = 15ns). to measure tx, ? adjust the delay on generator number 2 for a tx of several microseconds. this assures that the dac output has settled to its final wave. ? switch on the lsb (+5v) ? adjust the vlsb supply for 50% triggering at comparator out. this is indicated by traces of equal brightness on the oscilloscope display as shown in figure 4b. note dvm reading. ?switch to lsb to pulse (p) ? readjust the vlsb supply for 50% triggering as before, and note dvm reading. one lsb equals one tenth the difference in the dvm readings noted above. ? adjust the vlsb supply to reduce the dvm reading by 5 lsbs (dvm reads 10x, so this sets th e comparator to sense the final settled value minus 0.50 lsb). co mparator output disappears. ? reduce generator number 2 delay until comparator output reappears, and adjust for ?equal brightness?. ? measure tx from scope as show n in figure 4b. settling time equals tx + td, i.e., tx + 15ns. (a) ton, to final value +0.50 lsb (b) ton, to final value -0.50 lsb (c) toff, to final value +0.50 lsb (d) off, to final value -0.50 lsb table 1. operating modes and calibration mode circuit connections calibration output range pin 10 to pin 11 to resistor (r) apply input code adjust to set vo unipolar (see figure 2) 0 to +10v vo pin 10 1.43k all 0?s all 1?s r1 r2 0v +9.99756v 0 to +5v vo pin 9 1.1k all 0?s all 1?s r1 r2 0v +4.99878v bipolar (see figure 3) 10v nc vo 1.69k all 0?s all 1?s r3 r4 -10v +9.99512v 5v vo pin 10 1.43k all 0?s all 1?s r3 r4 -5v +4.99756v 2.5v vo pin 9 1.1k all 0?s all 1?s r3 r4 -2.5v +2.49878v
hs-565brh, hs-565beh 6 fn4607.4 may 7, 2012 other considerations grounds the hs-565brh, hs-565beh has two ground terminals, pin 5 (ref gnd) and pin 12 (pwr gnd). thes e should not be tied together near the package unless that point is also the system signal ground to which all returns are co nnected. (if such a point exists, then separate paths are required to pins 5 and 12). the current through pin 5 is near zero dc (note); but pin 12 carries up to 1.75ma of code - dependent current from bits 1, 2, and 3. the general rule is to connect pin 5 directly to the system ?quiet? point, usually called signal or analog ground. connect pin 12 to the local digital or power ground. then, of course, a single path must connect the analog/signal and digital/power grounds. note: current cancellation is a two step process within the hs-565brh, hs-565beh in which code dependent variations are eliminated, the resulting dc current is supplied internally. first an auxiliary 9-bit r-2r ladde r is driven by the complement of the dacs input code. together, the main and auxiliary ladders draw a continuous 2.25ma from the internal ground node, regardless of input code. part of the dc current is supplied by the zener voltage reference, and the remainder is sourced from the positive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5). layout connections to pin 9 (iout) on the hs-565brh, hs-565beh are most critical for high speed perf ormance. output capacitance of the dac is only 20pf, so a small change of additi onal capacitance may alter the op amp?s stability and affect settling time. connections to pin 9 should be short and few. component leads should be short on the side conne cting to pin 9 (as for feedback capacitor c). see the ?settling time? section on page 5. bypass capacitors power supply bypass capacitors on the op amp will serve the hs-565brh, hs-565beh also. if no op amp is used, a 0.01f ceramic capacitor from each supply terminal to pin 12 is sufficient, since supply curr ent variations are small. . figure 4a. figure 4b. vlsb supply 0.1 f dvm comparator out b c 10 90 200k + - 5 9 10 nc 11 8 2.5k 5k 5k 20v 20% bias turn on turn off 9.95k 2ma 12 hs-565brh d pulse generator no. 2 out 14 13 23 24 . . . . . . . . . . . . . 5v p pulse generator no. 1 sync in trig out out a ~100 khz strobe in lsb 50% digital input dac output comp. strobe comp. out ?equal brightness? +3v 0v 0v -400mv 2v 0.8v 4v 0v (turn off) a b c d 50% tx td = comparator delay settling time - 0.50 lsb
hs-565brh, hs-565beh 7 fn4607.4 may 7, 2012 die characteristics die dimensions: 179 mils x 107 mils x 19 mils interface materials: glassivation: type: alcu thickness: 8k ? 1k ? top metallization: type: al/copper thickness: 16k ? 2k ? substrate: bipolar di, backside finish: silicon assembly related information substrate potential: tie substrate to vref gnd additional information: worst case current density: 2.0 x 10 5 a/cm 2 transistor count: 200 metallization mask layout hs-565brh, hs-565beh vcc (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 (lsb) power gnd 20v span 10v span idac out bipolar 12 -vs vref in vref gnd vref out 3 nc 3 nc 1 a
hs-565brh, hs-565beh 8 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn4607.4 may 7, 2012 for additional products, see www.intersil.com/product_tree ceramic dual-in-line meta l seal packages (sbdip) notes: 1. index area: a notch or a pin one iden tification mark shall be located ad- jacent to pin one and shall be locat ed within the shaded area shown. the manufacturer?s identification shal l not be used as a pin one identi- fication mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead platin g and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d24.6 mil-std-1835 cdip2-t24 (d-3, configuration c) 24 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.290 - 32.77 - e 0.500 0.610 12.70 15.49 - e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.120 0.200 3.05 5.08 - q 0.015 0.075 0.38 1.91 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n24 248 rev. 0 4/94
hs-565brh, hs-565beh 9 fn4607.4 may 7, 2012 ceramic metal seal flat pack packages (flatpack) notes: 1. index area: a notch or a pin one iden tification mark shall be located ad- jacent to pin one and shall be locat ed within the shaded area shown. the manufacturer?s identification sha ll not be used as a pin one identi- fication mark. alternately, a tab (dim ension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m ap- plies to lead plating and finish th ickness. the maximum limits of lead dimensions b and c or m shall be m easured at the centroid of the fin- ished lead surfaces, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the menis- cus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and toleranci ng per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k24.a mil-std-1835 cdfp4-f24 (f-6a, configuration b) 24 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.640 - 16.26 3 e 0.350 0.420 9.14 10.67 - e1 - 0.450 - 11.43 3 e2 0.180 - 4.57 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n24 24- rev. 0 5/18/94
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